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CAT25C11/03/05/09/17
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM FEATURES
s 10 MHz SPI compatible s 1.8 to 6.0 volt operation s Hardware and software protection s Zero standby current s Low power CMOS technology s SPI modes (0,0 & 1,1)* s Commercial, industrial, automotive and extended s 100 year data retention s Self-timed write cycle
H
GEN FR ALO
EE
LE
A D F R E ETM
s 1,000,000 program/erase cycles
s 8-pin DIP/SOIC, 8/14-pin TSSOP and 8-pin MSOP s 16/32-byte page write buffer s Write protection
temperature ranges
- Protect first page, last page, any 1/4 array or lower 1/2 array
DESCRIPTION
The CAT25C11/03/05/09/17 is a 1K/2K/4K/8K/16K-Bit SPI Serial CMOS EEPROM internally organized as 128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst's advanced CMOS Technology substantially reduces device power requirements. The CAT25C11/03/05 features a 16-byte page write buffer. The 25C09/17 features a 32-byte page write buffer.The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C11/03/05/09/17 is designed with software and hardware write protection features including Block Write protection. The device is available in 8-pin DIP, 8-pin SOIC, 8/14-pin TSSOP and 8-pin MSOP packages.
PIN CONFIGURATION
TSSOP Package (U14, Y)
CS SO NC NC NC WP VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI
SOIC Package (S, V)
CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
DIP Package (P, L)
CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
CS SO
TSSOP Package (U, Y)
1 2 3 4 8 7 6 5 VCC HOLD SCK SI
WP VSS
MSOP Package (R, Z)*
CS SO WP VSS
1 2 3 4
8 7 6 5
BLOCK DIAGRAM
SENSE AMPS SHIFT REGISTERS
VCC
HOLD SCK
SI
PIN FUNCTIONS Pin Name
SO SCK WP VCC VSS CS SI HOLD NC
*CAT25C11/03 only
WORD ADDRESS BUFFERS
COLUMN DECODERS
Function
Serial Data Output Serial Clock Write Protect +1.8V to +6.0V Power Supply Ground Chip Select Serial Data Input Suspends Serial Input No Connect
STATUS REGISTER HIGH VOLTAGE/ TIMING CONTROL SO SI CS WP HOLD SCK I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC
CONTROL LOGIC
XDEC
EEPROM ARRAY
DATA IN STORAGE
* Other SPI modes available on request.
(c) 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1017, Rev. F
CAT25C11/03/05/09/17
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to VSS(1) .................. -2.0V to +VCC +2.0V VCC with Respect to VSS ................................ -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
(3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Min. 1,000,000 100 2000 100
Max.
Units Cycles/Byte Years Volts mA
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
TDR(3) VZAP(3) ILTH(3)(4)
D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol ICC1 ICC2 ISB ILI ILO VIL(5) VIH(5) VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC-0.2 VCC - 0.8 0.2 -1 VCC x 0.7 Min. Typ. Max. 5 3 0 2 3 VCC x 0.3 VCC + 0.5 0.4 Units mA mA A A A V V V V V V 2.7VVCC<5.5V IOL = 3.0mA IOH = -1.6mA 1.8VVCC<2.7V IOL = 150A IOH = -100A VOUT = 0V to VCC, CS = 0V Test Conditions VCC = 5V @ 5MHz SO=open; CS=Vss VCC = 5.5V FCLK = 5MHz CS = VCC VIN = VSS or VCC
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. (5) VILMIN and VIHMAX are reference values only and are not tested.
Doc. No. 1017, Rev. F
2
CAT25C11/03/05/09/17
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA=25C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol COUT CIN
Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD)
Max. 8 6
Units pF pF
Conditions VOUT=0V VIN=0V
A.C. CHARACTERISTICS Limits 1.8V-6.0V SYMBOL PARAMETER tSU tH tWH tWL fSCK tLZ tRI(1) tFI(1) tHD tCD tWC(3) tV tHO tDIS tHZ tCS tCSS tCSH tWPS tCSH
(1) (2)
2.5V-6.0V Max. 20 20 75 75
4.5V-5.5V Min. 20 20 40 40 Max. ns ns ns ns 10 50 2 2 40 40 MHz ns s s ns ns 5 40 0 ms ns ns 75 50 100 100 100 50 50 ns ns ns ns ns ns ns
Test UNITS Conditions VIH = 2.4V CL = 100pF VOL = 0.8V VOH = 2.0v
Min. 50 50 250 250 DC
Max. Min.
Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Write Cycle Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS Hold Time WP Setup Time CS Hold Time
1 50 2 2
DC
5 50 2 2
DC
CL = 50pF (note 2)
100 100 10 250 0 250 150 500 500 500 150 150
40 40 5 75 0 75 50 100 100 100 50 50
CL = 100pF
(3)
This parameter is tested initially and after a design or process change that affects the parameter. AC Test Conditions: Input Pulse Voltages: 0.3VCC to 0.7VCC Input rise and fall times: 10ns Input and output reference voltages: 0.5VCC Output load: current source IOL max/IOH max; CL = 50pF tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
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Doc. No. 1017, Rev. F
CAT25C11/03/05/09/17
FUNCTIONAL DESCRIPTION
The CAT25C11/03/05/09/17 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C11/03/05/09/17 to interface directly with many of today's popular microcontrollers. The CAT25C11/03/05/09/17 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define Figure 1. Sychronous Data Timing
VIH
the operation to be performed.
PIN DESCRIPTION
SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C11/03/05/09/17.Input data is latched on the rising edge of the serial clock for SPI modes (0, 0 & 1, 1). SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C11/03/05/09/17. During a read cycle, data is shifted out on the falling edge of the serial clock for
tCS
CS
VIL tCSS VIH tCSH
SCK
VIL tSU VIH
tWH tH
tWL
SI
VIL
VALID IN
tRI
tFI
tV VOH
tHO
tDIS HI-Z
SO
VOL
HI-Z
Note: Dashed Line= mode (1, 1) - - - -
INSTRUCTION SET Instruction WREN WRDI RDSR WRSR READ WRITE Power-Up Timing(2)(3) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max. 1 1 Units ms ms Opcode 0000 0110 0000 0100 0000 0101 0000 0001 0000 X011(1) 0000 X010(1) Operation Enable Write Operations Disable Write Operations Read Status Register Write Status Register Read Data from Memory Write Data to Memory
Note: (1) X=0 for 25C11, 25C03, 25C09, 25C17. X=A8 for 25C05 (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Doc. No. 1017, Rev. F
4
CAT25C11/03/05/09/17
and forces the devices into a Standby Mode (unless an internal write operation is underway) The CAT25C11/03/ 05/09/17 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. WP: WP Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to "1", all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle as already been initiated, WP going low will have no effect on any write Address Don't Care Bits A7 -- -- A15 - A10 A15 - A11 # Address Clock Pulse 8 8 8 16 16
SPI modes (0,0 & 1,1). SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the 25C11/03/05/09/17. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK for SPI modes (0,0 & 1,1). CS: CS Chip Select CS is the Chip select pin. CS low enables the CAT25C11/ 03/05/09/17 and CS high disables the CAT25C11/03/05/ 09/17. CS high takes the SO output pin to high impedance BYTE ADDRESS Device CAT25C11 CAT25C03 CAT25C05 CAT25C09 CAT25C17 STATUS REGISTER 7 WPEN 6 1 5 1 4 BP2 Address Significant Bits A6 - A0 A7 - A0 A7 - A0 (A8 = X bit from Opcode) A9 - A0 A10 - A0
3 BP1
2 BP0
1 WEL
0 RDY
MEMORY PROTECTION BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Non-Protection Q1 Protected Q2 Protected Q3 Protected Q4 Protected H1 Protected P0 Protected Pn Protected Q1 Q2 Q3 Q4 H1 P0 Pn 25C11 00-1F 20-3F 40-5F 60-7F 00-3F 00-0F 70-7F 25C03 00-3F 40-7F 80-BF C0-FF 00-7F 00-0F F0-FF 25C05 000-07F 080-0FF 100-17F 180-1FF 000-0FF 000-00F 25C09 000-0FF 100-1FF 200-2FF 300-3FF 000-1FF 000-01F 25C17 000-1FF 200-3FF 400-5FF 600-7FF 000-3FF 000-01F 7E0-7FF
1F0-1FF 3E0-3FF
WRITE PROTECT ENABLE OPERATION WPEN 0 0 1 1 X X WP X X Low Low High High WEL 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected
5
Unprotected Blocks Protected Writable Protected Writable Protected Writable
Status Register Protected Writable Protected Protected Protected Writable
Doc. No. 1017, Rev. F
CAT25C11/03/05/09/17
operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. Figure 10 illustrates the WP timing sequence during a write operation. HOLD: HOLD Hold HOLD is the HOLD pin. The HOLD pin is used to pause transmission to the CAT25C11/03/05/09/17 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. HOLD should be held high any time this function is not being used. HOLD may be tied high directly to VCC or tied to VCC through a resistor. Figure 9 illustrates hold timing sequence.
03/05/09/17 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only the WEL (Write Enable) bit indicates the status of the write enable latch. When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. The BP0, BP1 and BP2 bits indicate which part of the memory array is currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect from one page to as much as half the entire array. Once the three protection bits are set the associated memory can be read but not written until the protection bits are reset. These bits are non volatile. The WPEN (Write Protect Enable) is an enable b it for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register, (including the block protect bits
STATUS REGISTER
The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C11/
Figure 2. WREN Instruction Timing
CS
SK
SI
0
0
0
0
0
1
1
0
SO
Note: Dashed Line= mode (1, 1) - - - -
HIGH IMPEDANCE
Figure 3. WRDI Instruction Timing
CS
SK
SI
0
0
0
0
0
1
0
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) - - - -
Doc. No. 1017, Rev. F
6
CAT25C11/03/05/09/17
and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero.
DEVICE OPERATION
Write Enable and Disable The CAT25C11/03/05/09/17 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C11/03/05/09/17, followed by the 16-bit address for 25C09/17 (only 10-bit addresses are used for 25C09, 11-bit addresses are used for 25C17. The rest of the bits are don't care bits) and 8-bit address for 25C11/03/05 (for the 25C05, bit 3 of the read data instruction contains address A8).
After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. If a non-volatile write is in progress, the RDSR instruction returns a high on SO. When the non-volatile write cycle is completed, the status register data is read out. WRITE Sequence The CAT25C11/03/05/09/17 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25C11/03/05/09/17. The device goes into Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25C11/03/05/09/17. The CS must be brought high
Figure 4. Read Instruction Timing
CS 0 SK
OPCODE
1
2
3
4
5
6
7
8
9
10
20
21
22
* 23
24
25
26
27
28
29
* 30
BYTE ADDRESS* 0 1 1 AN A0
DATA OUT
SI
0
0
0
0
X*
SO
HIGH IMPEDANCE
7
MSB
6
5
4
3
2
1
0
*Please check the Byte Address Table. *X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05.
Note: Dashed Line= mode (1, 1) - - - -
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Doc. No. 1017, Rev. F
CAT25C11/03/05/09/17
enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field. Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address for 25C09/17. (only 10-bit addresses are used for 25C09, 11-bit addresses are used for 25C17. The rest of the bits are don't care bits) and 8-bit address for 25C11/03/05 (for the 25C05, bit 3 of the read data instruction contains address A8). Programming will start after the CS is brought high. Figure 6 illustrates byte write sequence. Page Write The CAT25C11/03/05/09/17 features page write capability. After the initial byte, the host may continue to write after the WREN instruction to enable writes to thee Figure 5. RDSR Instruction Timing
CS 0 SCK
OPCODE
device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write up to 16 bytes of data to the CAT25C11/03/05 and 32 bytes of data for 25C09/17. After each byte of data received, lower order address bits are internally incremented by one; the high order bits of address willremain constant.The only restriction is that the X (X=16 for 25C11/03/05 and X=32 for 25C09/17) bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will "roll over" to the first address of the page and overwrite any data that may have been written. The CAT25C11/03/05/09/17 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. To write to the status register, the WRSR instruction should be sent. Only Bit 2, Bit 3, Bit 4 and Bit 7 of the status register can be written using the write status register instruction. Figure 7 illustrates the sequence of writing to status register.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SI
0
0
0
0
0
1
0
1
DATA OUT
SO
HIGH IMPEDANCE
7
MSB
6
5
4
3
2
1
0
Note: Dashed Line= mode (1, 1) - - - -
Figure 6. Write Instruction Timing
CS 0 SK
OPCODE
1
2
3
4
5
6
7
8
21
22
* 23
24
25
26
27
28
29
30
* 31
BYTE ADDRESS* 0 1 0 AN A0 D7 D6 D5
DATA IN
SI
0
0
0
0
X*
D4
D3
D2
D1
D0
SO
HIGH IMPEDANCE
*Please check the Byte Address Table X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05
Note: Dashed Line= mode (1, 1) - - - -
Doc. No. 1017, Rev. F
8
CAT25C11/03/05/09/17
DESIGN CONSIDERATIONS The CAT25C11/03/05/09/17 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the CAT25C11/03/05/09/17 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and programming is continued. On power up, SO is in a high impedance. If an invalid op code is received, no data will be shifted into the CAT25C11/03/ 05/09/17, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again.
Figure 7. WRSR Instruction Timing
CS 0 SCK
OPCODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DATA IN
SI
0
0
0
0
0
0
0
1
7
MSB
6
5
4
3
2
1
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) - - - -
Figure 8. Page Write Instruction Timing
CS
0 SK
1
2
3
4
5
6
7
8
21
22
23 24-31
32-39
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
OPCODE
BYTE ADDRESS* 0 1 0 AN A0
Data Byte 1
DATA IN Data Byte 2 Data Byte 3 Data Byte N 0 7..1
SI
0
0
0
0
X*
SO
HIGH IMPEDANCE
*Please check the Byte Address Table. *X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05
Note: Dashed Line= mode (1, 1) - - - -
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Doc. No. 1017, Rev. F
CAT25C11/03/05/09/17
Figure 9. HOLD Timing
CS tCD SCK tHD HOLD tHZ SO
HIGH IMPEDANCE
tCD
tHD
tLZ
Figure 10. WP Timing
tWPS
tWPH
CS
tCSH
SCK
WP
WP
Note: Dashed Line= mode (1, 1) - - - -
Doc. No. 1017, Rev. F
10
CAT25C11/03/05/09/17
ORDERING INFORMATION
Prefix CAT Device # 25C17 Suffix S I Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) A = Automotive (-40C to +105C) E = Extended (-40C to +125C) -1.8 TE13
Optional Company ID
Product Number 25C17:16K 25C09: 8K 25C05: 4K 25C03: 2K 25C11: 1K
Tape & Reel TE13: 2000/Reel
Package P = 8-pin PDIP R = 8-pin MSOP2 S = 8-pin SOIC U = 8-pin TSSOP U14 = 14-pin TSSOP L = PDIP (Lead free, Halogen free) V = SOIC, JEDEC (Lead free, Halogen free) X = SOIC, EIAJ (Lead free, Halogen free) Y = TSSOP (Lead free, Halogen free) Z = MSOP2 (Lead free, Halogen free)
Operating Voltage Blank (Vcc=2.5 to 6.0V) 1.8 (Vcc=1.8 to 6.0V)
Notes: (1) The device used in the above example is a 25C17SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) (2) CAT25C11 and CAT25C03 only.
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
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11
Publication #: Revison: Issue date: Type:
1017 F 9/24/02 Final
Doc. No. 1017, Rev. F

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